Audio Noise Supression using Magnitude Subtraction Method

This paper proposes an efficient hardware architecture for the spectral subtraction algorithm applied to speech enhancement. Spectral subtraction algorithm is widely used in audio de-noising applications. The proposed architecture uses a novel approach to estimate environmental noise from speech adaptively. After estimating the noise from the input speech the noise samples are subtracted, making it noise free. In this design we have two principal blocks, the noise estimation-subtraction block and the phase block, which are executed concurrently exploiting the parallel logic blocks of field programmable gate array (FPGA). We have implemented our design on Spartan6 LX45 FPGA, which also meets the high speed requirements. Resource utilization and delay information for the different blocks in our design are presented. Our proposed hardware implementation shows a better SNR value compared to the original software implementation. To the best of our knowledge, this work is the first of its kind of implementation in regards to FPGA based hardware design for adaptive noise filtering in speech.

Project Introduction

Stationary noise when added with speech degrades theperformance of the original speech signal. Related researchworks have been done for the last three decades in regardsto noise reduction of speech signal. The spectral subtractionalgorithm is a commonly known technique, originally intro-duced by Boll for speech enhancement. A better versionwas introduced by Berouti et al. for the musical noisereduction. Spectral subtraction method has low computationalcomplexity and can be performed in real time. The princi-ple behind spectral subtraction technique is to subtract themagnitude spectrum of noise from the spectrum of the noisyspeech. While this method reduces the broadband noise, italso introduces an annoying noise. This phenomenon can beexplained by signal-to-noise ratio (SNR) estimation errorsleading to spurious peaks in the processed spectrum.